1. Field of the Invention
The present invention relates to a high degree of integration of a semiconductor memory device and, more specifically, to a semiconductor memory device including memory cells formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
In a semiconductor integrated circuit, especially, a semiconductor memory device such as a DRAM, the area of memory cells has recently been decreased more and more in accordance with a remarkably high degree of integration. This necessitates miniaturizing charge storage layers constituting the memory cells, transistors, and element isolation regions each formed between the memory cells, thus causing various problems. For example, if the area of the charge storage layers is reduced, a sufficient amount of charge cannot be stored, the transistors are difficult to control, and an isolation withstand voltage cannot be obtained sufficiently between the memory cells.
Various methods for resolving the above problems have been considered and put to practical use. For instance, the area of the charge storage layers can be secured by forming the layers above both the transistors and bit lines. If the memory cells are formed on an island-like semiconductor substrate insulatively formed in an insulation film, the isolation withstand voltage can be enhanced, and the short channel effect can be suppressed, thereby improving in controllability of the transistors.
A conventional stacked capacitor type memory cell adopting the above method has, for example, the following structure. An insulation layer is formed on a semiconductor substrate, and a monocrystalline silicon layer is formed on the insulation layer. To form the monocrystalline silicon layer on the insulation layer is called the SOI structure. The monocrystalline silicon layer is surrounded with an element isolation region reaching the insulation layer thereby to form an element region. The element region is isolated like an island, and a gate insulation film is selectively formed in the isolated element region. A gate electrode is formed on the gate insulation film, and two diffusion layers (source and drain regions) are formed on the surface of the element region so as to interpose the gate electrode therebetween. These gate insulation film, gate electrode and diffusion layers constitute a transistor. One of the source and drain regions of the transistor is connected to a bit line formed above the gate electrode. The other one of the source and drain regions is connected to a storage electrode formed thereon. The storage electrode is opposite to a plate electrode formed higher than the bit line, thus constituting a capacitor (see FIG. 15).
In the conventional memory cell, signal data transmitted through the bit line is stored in the storage electrode through the transistor, and the data stored in the electrode is read out and supplied to the bit line through the transistor.
As described above, in the conventional memory cell, since a transistor is formed on the semiconductor substrate isolated in the insulation film, the short channel effect can be suppressed and the element isolation withstand voltage can be increased. Since, furthermore, a capacitor can be formed on the gate electrode and the bit line, the area for the capacitor can be secured. Consequently, various problems due to miniaturization of memory cells can be resolved.
However, in the conventional memory cell, the storage electrode is formed so as to cover the bit line with the insulation film interposed therebetween, a very deep connecting hole has to be opened in order to connect the storage electrode to one of the source and drain regions. The miniaturization of memory cells makes it very difficult to prevent the storage electrode from being short-circuited with the gate electrode and the bit line, and the connecting hole is required to be very correctly self-aligned with the gate electrode and the bit line.
Conventionally, it is considerably difficult to manufacture a memory cell having an area enough to form a capacitor and having a transistor improved in element isolation withstand voltage and in controllability, without causing the storage electrode to be short-circuited with the gate electrode and the bit line.